搜索资源列表
m.e-lab
- vhdl verilog code for alu operation pll,biy sliced processor
Lab4
- Lab 4 Verilog implementation of ALU
ALUPVERILOG
- 用verilog HDL语言实现ALU 运行于quartus-ALU using verilog HDL language to run on quartus
jf
- verilog编写的alu模块4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出-Verilog modules prepared by the ALU4bit ALU (arithmetic logic unit) design is given in the design of alu input and ou
SRC
- 流水线cpu 顶层模块verilog源代码，和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
F_ADD
- 使用硬體描述語言verilog的運算單元-it s an ALU using verilog to design
SourceCode
- That s a bunch of ALU control code for MIPS pipelined in Verilog!
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
alu_sequence_detector_1101
- It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
cluster
- ALU Cluster using VERILOG.
alu_sequence_detector_1101
- It is verilog based implementation of ALU and sequence detector for detecting sequence 1101
day8_alu_design
- this verilog code for designing ALU in fpga.-this is verilog code for designing ALU in fpga.
lab2.tar
- 32 bit alu using structural verilog. has test benches t-32 bit alu using structural verilog. has test benches too
aa
- Verilog实现运算器ALU的编程，加减（16位）乘除（16*16，32/16）-Verilog to achieve calculator ALU programming, and (16) and (16*16, 32/16)
FloatALU
- 用Verilog HDL实现的IEEE754浮点数加减乘除法器-float number alu
CPU
- 用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.
ALU_VERILOG_COCOTB
- ALU written in Verilog HDL and tester written in python using the cocotb library
计算器
- 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)